1. Field of the Invention
The present invention relates to a display device, and more particularly, to a drive circuit of a display device and a method for driving the display device.
2. Discussion of the Related Art
Recently, various flat display devices have been developed that can eliminate the bulky and heavy structures associated with cathode ray tube based displays. These flat panel display devices include liquid crystal displays, field emission displays, plasma display panels, and light emitting diode based displays.
Typically, a liquid crystal display includes a thin film transistor substrate, a color filter substrate separated by a uniform distance from the thin film transistor substrate, and a liquid crystal layer formed between the substrates. A plurality of liquid crystal cells are arranged in regions defined by the crossings of an associated one of a plurality of data lines and an associated one of a plurality of gate lines. A thin film transistor, which is a switch element, is formed at each liquid crystal cell. In a liquid crystal display having the above-described structure, an electric field is generated at each liquid crystal cell in accordance with a data signal to adjust the transmittance of light through the liquid crystal layer. By controlling the transmittance of light through the liquid crystal layer, a desired image is displayed on the liquid crystal display.
Hereinafter, a liquid crystal display of the related art will be described with reference to the FIGS. 1 and 2 of the accompanying drawings.
FIG. 1 is a circuit diagram illustrating a drive circuit used in a liquid crystal display of the related art. FIG. 2 is a timing diagram of sampling scan pulses output from the shift register of the drive circuit shown in FIG. 1.
As shown in FIG. 1, the drive circuit of the liquid crystal display of the related art includes a shift register SR for sequentially outputting sampling scan pulses SP1 to SPm, a data transfer line DT for transferring an analog data signal Data having information as to an image, and a switch unit 10 for sampling the analog data signal Data from the data transfer line DT in response to a sampling scan pulse output from the shift register SR, and outputting the sampled signal.
The switch unit 10 includes a plurality of switches SW1 to SWm. Each of the switches SW1 to SWm is a 3-terminal switch. That is, each of the switches SW1 to SWm has a first terminal connected to the shift register SR to control the switch, a second terminal connected to the data transfer line DT, and a third terminal connected to an associated data line DL1 to DLm of the display.
The switches SW1 to SWm are sequentially turned on in response to the first to m-th scan pulses SP1 to SPm sequentially supplied from the shift register SR, respectively. That is, the first to m-th sampling scan pulses SP1 to SPm are sequentially supplied to the first to m-th switches SW1 to SWm, respectively, and as a result, the first to m-th switches SW1 to SWm are sequentially turned on. Further, when one of the switches SW1 to SWm is in an ON state, the remaining ones of the switches SW1 to SWm are maintained in an OFF state.
When in an ON state, each of the switches SW1 to SWm samples the analog data signal data supplied to the data transfer line DT, and supplies the sampled signal to the associated data line. Thus, sampled analog data signals are supplied to the data lines DL1 to DLm of the display in a sequential manner. Analog data signals associated with one horizontal line are supplied to the data lines DL1 to DLm in a sequential manner within one horizontal period 1H.
The sampled analog data signals respectively supplied to the data lines DL1 to DLm are then supplied to a plurality of pixel cells connected in common to one gate line in a sequential manner, respectively. A gate signal GS is supplied to the gate line, in order to sustain the gate line in a high-level state for one horizontal period.
Although not shown, each pixel cell includes a thin film transistor connected between an associated one of the gate lines and an associated one of the data lines, and a pixel electrode connected to the thin film transistor.
The thin film transistor of each pixel cell is turned on in response to a high-level gate signal GS from the associated gate line. In an ON state thereof, the thin film transistor supplies the sampled analog data signal from the associated data line to the pixel electrode of the associated pixel cell.
Because the first switch SW1 is the first of the switches to be turned on during a horizontal period, the first-sampled analog data signal is supplied to the first data line DL1. As a result, the sampled analog data signal is applied to the first pixel cell for a period (i.e. a data sustain time) longer than the period of application to pixel cells via the remaining switches. That is, the thin film transistor of the first pixel cell is maintained in an ON state for nearly a complete horizontal period after the point of time when the first pixel cell receives the sampled analog signal. Accordingly, the data sustain time of the first pixel cell of a horizontal line is longer than that for the remaining pixel cells in the horizontal line.
On the other hand, the last-sampled analog data signal is supplied latest to the m-th data line DLm because the m-th switch SWm is the last to be turned on. As a result, the m-th pixel cell connected to the m-th data line DLm sustains the sampled analog data signal for the shortest period of all of the pixel cells in a horizontal line. That is, the thin film transistor of the m-th pixel cell is maintained in an ON state for a relatively short time after the point of time when the m-th pixel cell receives the sampled analog signal. Accordingly, the data sustain time of the m-th pixel cell is shortest.
The variation in data sustain times may result in a brightness difference among the pixel cells of the display and degradation of the picture quality of the display.